Key Features
The SerDes is easy because it includes embedded signal conditioning blocks like transmit de-emphasis, receive equalization and DC-balancing, they do not require external system intervention for alignment. In addition, no reference clock is required at the receiver making the clocking scheme simple.
The SerDes is also high performance because it drives inexpensive cables like CAT-5/CAT-6 for longer distances at data rates up to 3.125 Gbps. The National DS32ELX421/0124 innovative PLL and CDR architecture ensure that the SerDes chipset has low output jitter and high tolerance of input jitter.
- Half EXP module format
- Wide serial data rate 1.25 Gbps to 3.125 Gbps
- 5-bit LVDS parallel interface to FPGA
- Integrated signal conditioning
- Fully featured FPGA design included
- Xilinx BERT tester with error insertion
- 12 patterns available for BERT testing
- MicroBlaze™ CPU design
- Terminal interface
- Link status registers/LEDs
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Kit Includes
- EXP High-Speed Serializer/Deserializer Module
- Downloadable documentation and reference design
Attached Files Additional Information
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Get Behind the Wheel of the EXP High-Speed SerDes Module and take a quick video tour to see the board in action.
Click the Behind the Wheel icon to start your drive. Run time: 5:35
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