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Avnet EM > Design > Training And Events > On-Demand Xilinx SpeedWay Design Workshops™

On-Demand Xilinx SpeedWay Design Workshops™

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Now Available On-Demand

Avnet Electronics Marketing introduces the on-demand series of Xilinx® SpeedWay Design Workshops™ for designers of electronic applications based on the Xilinx Zynq®‑7000 All Programmable (AP) SoC Architecture. Taught by Avnet technical experts, these on-demand courses combine informative presentations with do-it-yourself labs supported by the ZedBoard™ and MicroZed™ development platforms. The training is recommended equally for engineers who want to gain experience with the tools and techniques that can be used to implement the Zynq‑7000 All Programmable SoC family.

 
  • OVERVIEW WHO SHOULD WATCH?
    Developing Zynq®-7000 All Programmable SoC Software

    The Xilinx Software Development Kit (SDK) offers everything necessary to make Xilinx Zynq®-7000 All Programmable SoC software application development easy. This course covers these capabilities, including BSP creation, built-in drivers, example C code, interrupts, debugging, flash programming, and where to get more help. By making use of a pre-built Zynq®-7000 All Programmable SoC hardware platform, designers can focus on learning SDK. As a prerequisite to the “Developing Zynq®-7000 All Programmable SoC Hardware” course, this course provides the SDK training necessary to be successful in the Hardware course, where designers learn how the hardware platform was built.

    Note: A ZedBoard or MicroZed are necessary to complete the labs

    Designers who:

    • Are familiar with basic embedded design and C programming
    Developing Zynq®-7000 All Programmable SoC Hardware

    This course demonstrates the hardware and software flows for creating your first Xilinx Zynq®-7000 All Programmable SoC design. Through a series of presentations and labs, hardware and firmware engineers will learn all the required steps for creating a complete Zynq®-7000 All Programmable SoC design on either ZedBoard™ or MicroZed™. It covers the architecture of the ARM® Cortex™-A9 processing system (PS) and the integration of programmable logic (PL). The course also details the individual components that comprise the PS, I/O peripherals, clocking, interrupt, AXI interfaces and memory controllers. Emphasis is placed on efficient PL-to-PS interfacing including integration of custom PL-based IP. To complete the design cycle, the critical steps of hardware debugging techniques are also shown.

    Note: A ZedBoard or MicroZed are necessary to complete the labs

    Designers who:

    • Have completed the “Developing Zynq®-7000 All Programmable SoC Software” course or have equivalent knowledge
    • Are familiar with the Zynq®-7000 All Programmable SoC architecture
    PetaLinux for the Zynq®-7000 All Programmable SoC

    This intermediate-level course provides embedded systems developers with experience in creating an embedded Linux operating system on a Xilinx Zynq®-7000 All Programmable SoC. Based on the PetaLinux Software Development Kit (SDK), the course offers students experience in building the environment and booting the system using a basic Zynq®-7000 All Programmable SoC design. This course also introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging/profiling options for embedded Linux platforms.

    Note: A ZedBoard or MicroZed are necessary to complete the labs

    Designers who:

    • Have completed the “Developing Zynq®-7000 All Programmable SoC Software” and “Developing Zynq®-7000 All Programmable SoC Hardware” courses or have equivalent knowledge
    • Are familiar with the Zynq®-7000 All Programmable SoC architecture
    Designing Accelerators for the Zynq®-7000 All Programmable SoC

    System-on-Chip designs offer the unique advantage of providing custom built accelerators to increase system performance. This intermediate-level course introduces designers to the design flow required in identifying software bottlenecks and creating custom hardware accelerators in the Programmable Logic (PL) portion of the Xilinx Zynq®-7000 All Programmable SoC. Students will use profiling techniques to identify acceleration opportunities and simulate and synthesize a C-based accelerator for the PL using the Xilinx Vivado® HLS tool. Designers will use the IP Integrator feature in the Vivado Design Suite to perform final integration of the accelerator into the PL and identify the most appropriate interface for connection with the processing system. As a last step, the custom accelerator is integrated back into the software application flow for final verification of execution performance improvement.

    Note: A ZedBoard or MicroZed are necessary to complete the labs

    Designers who:

    • Have completed the “Developing Zynq®-7000 All Programmable SoC Software” and “Developing Zynq®-7000 All Programmable SoC Hardware” courses or have equivalent knowledge

All Locations

All Event Locations & Dates

  • Web Seminar
    • 7/25/2014 - 7/25/2015
    • 12:00 AM - 12:00 AM
    • ,
    • Attendance Cost: $0
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